VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing

CMOS Standard Cells Characterization for IDDQ Testing

This paper describes the CMOS standard cells characterization methodology for IDDQ testing. Defect statistics was taken into account and critical area approach was used to generate compact test sets. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. Experimenta...

Experimental Results for IDDQ and VLV Testing

An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed the Stage 1 tests were packaged for further investigation. This paper describes the experimental setup and the preliminary results for the final package test. We focus on the correlation among various defect classes, i...

Built-in current sensor for IDDQ testing

This paper presents the implementation of a built-in current sensor for DDQ testing. In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) ena...

Combination of Iddq Testing and High Level Atpg

T est generation for today’s complex digital cir cuits is an extr emely computation intensive task. The search space of ATPG can be reduced by starting from higher level circuit descriptions. The integration of alternate testing methodology IDDQ testing is suggested for increasing the efficiency of a high level VHDL based test generator.

Testing For Efficiency Wages In Iran